Non-volatile memory is memory that can continue to store data after power is no longer provided to the memory. “Flash memory,” called this because data can be erased from multiple memory cells simultaneously, is an example of non-volatile memory. A typical flash memory comprises an array of memory cells arranged in rows and columns. The array is divided into blocks of memory cells, with 2048 or 4096 blocks in a typical flash memory device. Although each of the cells within a block can be electrically programmed to store data individually, data is erased from the cells at the block level.
A common example of flash memory is NAND flash memory. The array of memory cells for NAND flash memory devices are arranged such that a control gate of each memory cell of a row of the array is connected to a word line. However, each memory cell is not directly connected to a column bit line. Instead, the memory cells of the array are arranged together in strings (“NAND strings”), with the memory cells connected together in series, source to drain, between a source line and a column bit line. The NAND strings in each block typically have as many as 32 memory cells between the source line and the column bit line.
The memory array for NAND flash memory devices is accessed by a row decoder activating a row of memory cells by selecting the word line connecting the control gates of the memory cells. In addition, the word lines connected to the control gates of unselected memory cells of each string are driven so that the respective memory cell passes current in a manner that is unrestricted by their stored data values. Current then flows from the source line to the column bit line through each series connected string, restricted only by the selected memory cells of each string. This places the current-encoded data values of the row of selected memory cells on the column bit lines to be sense and amplified before being output as data, as well known.
After memory devices have been fabricated, they normally undergo testing to determine if they are functioning properly. It is not uncommon to find that many memory cells in the device are defective. For example, in flash memory device, it is common for functional testing to reveal that one or more blocks of memory cells are defective. In order to increase the yield from each semiconductor die, memory devices, including flash memory devices, are normally manufactured with extra columns and extra blocks of memory cells, which are sometimes referred to as “redundant columns” and “redundant blocks,” respectively. When a column or block of memory cells is found to be defective during testing, the defective column or block may be repaired by substituting a redundant column or block of memory cells. This is typically accomplished by programming a bank of fuses or anti-fuses with the address of the defective column or block. When an attempt is made to access the defective column or block, the corresponding address is detected, and the access is redirected to the redundant column or block, respectively.
The ability to perform post-fabrication repair of defective flash memory devices increases the die yield because it allows such devices to be sold. To further increase die yield and thereby minimize the cost of flash memory devices, standard specifications for NAND flash memory allow a manufacturer to sell NAND flash devices having a percentage of defective blocks of memory, which are referred to as “initial bad blocks” of memory. The bad blocks do not affect the performance of good blocks of memory because each block is independently accessible.
Generally the process of identifying initial bad blocks occurs during testing by the manufacturer. A conventional manner of marking the bad blocks is to program specific locations within each bad block with data that is used to indicate that the block is defective. Upon use of the memory device, a bad block disable process is performed. During this process, the specific locations are queried to identify which blocks of memory are bad. Control logic included in the memory device identifies the bad blocks by checking for the data that is indicative of a bad block. If such data is present, the block can be disabled using a conventional technique of setting a latch in the respective block decoder circuits for the bad block. Setting the latch prevents access to the bad block and provides a hardware mechanism for disabling bad blocks prior to operation. Although the technique of programming bad blocks with indicating data is effective in marking initial bad blocks, some users choose not to read the array for the bad block information prior to use, and simply erase the entire array. As a result, the data programmed to identify the bad blocks are erased, thus, eliminating any way to identify which blocks are bad after the erasing process. Also, this process requires that the user be involved in identifying of bad blocks and ensuring that they are not accessed. The user must therefore adapt a system containing the flash memory device to carry out these functions. Furthermore, if these functions are performed improperly, the flash memory device may provide erroneous data.
One approach to identifying bad blocks even in the case where the entire memory array is erased prior to use is to program initial bad block information in a user-inaccessible memory that is separate from the flash memory array. One technique is to program the initial bad block information into specific circuits designed to store this information. An example of this type of circuit is described in U.S. Pat. No. 5,864,499 to Roohparvar et al. The circuits described therein are small arrays of non-volatile memory cells having dedicated sense amplifiers. The memory cells can be programmed and function as “fuses” to store information identifying the initial bad blocks. One problem resulting from this approach is that as the number of memory blocks in a memory device increases, and there are a greater absolute number of bad blocks, the number of the dedicated “fuse circuits” must also increase. The additional fuse circuits occupy more space on the die, which is generally undesirable.
There is therefore a need for a system and method for identifying initial bad blocks and remapping accesses to initial bad blocks in a manner that is transparent to the user and does not require a large number of dedicated fuse circuits even though the memory device contains a large number of potentially defective blocks.